Zeljko Zilic grāmatas
Verification by Error Modeling: Using Testing Techniques in Hardware Verification
Zeljko Zilic, Katarzyna Radecka
-30% ar kodu BOOKS
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Verification by Error Modeling: Using Testing Techniques in Hardware Verification
Zeljko Zilic, Katarzyna Radecka
-30% ar kodu BOOKS
Piegādātāja noliktavā
Generating Hardware Assertion Checkers: For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line Monitoring
-30% ar kodu BOOKS
Piegādātāja noliktavā
Accelerating Test, Validation and Debug of High Speed Serial Interfaces
-30% ar kodu BOOKS
Piegādātāja noliktavā
Generating Hardware Assertion Checkers: For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line Monitoring
-30% ar kodu BOOKS
Piegādātāja noliktavā
Accelerating Test, Validation and Debug of High Speed Serial Interfaces
-30% ar kodu BOOKS
Piegādātāja noliktavā