Bezmaksas piegāde pasūtījumiem virs 29€

  • check 10+ miljoni grāmatu
  • check Jaunumi katru dienu
  • check Vairāk nekā 1 miljons klientu mums uzticas
  • check Labas cenas un atlaides
  • check Piegāde visā Eiropā

The e Hardware Verification Language - Sunita Joshi,Sasan Iman

angļu valoda
2004-05-28
221,75 € 369,58 €

-40% ar kodu BOOKS

Piegādātāja noliktavā

Piegāde 17-23 darba dienu laikā

30 dienu atgriešanas politika

I am glad to see this new book on the e language and on verification. I am especially glad to see a description of the e Reuse Methodology (eRM). The main goal of verification is, after all, finding more bugs quicker using given resources, and verification reuse (module-to-system, old-system-to-new-system etc. ) is a key enabling component. This book offers a fresh approach in teaching the e hardware verifi ... Pilns apraksts

Jums varētu patikt arī

Aprašymas

I am glad to see this new book on the e language and on verification. I am especially glad to see a description of the e Reuse Methodology (eRM). The main goal of verification is, after all, finding more bugs quicker using given resources, and verification reuse (module-to-system, old-system-to-new-system etc. ) is a key enabling component. This book offers a fresh approach in teaching the e hardware verification language within the context of coverage driven verification methodology. I hope it will help the reader und- stand the many important and interesting topics surrounding hardware verification. Yoav Hollander Founder and CTO, Verisity Inc. Preface This book provides a detailed coverage of the e hardware verification language (HVL), state of the art verification methodologies, and the use of e HVL as a facilitating verification tool in implementing a state of the art verification environment. It includes comprehensive descriptions of the new concepts introduced by the e language, e language syntax, and its as- ciated semantics. This book also describes the architectural views and requirements of verifi- tion environments (randomly generated environments, coverage driven verification environments, etc. ), verification blocks in the architectural views (i. e. generators, initiators, c- lectors, checkers, monitors, coverage definitions, etc. ) and their implementations using the e HVL. Moreover, the e Reuse Methodology (eRM), the motivation for defining such a gui- line, and step-by-step instructions for building an eRM compliant e Verification Component (eVC) are also discussed.

Vairāk informācijas

Autors Sunita Joshi, Sasan Iman
Izdevējs Springer US
Izlaides gads 2004
Vāka tips Cietais vāks
EAN 9781402080234
Rakstiet savu atsauksmi
Jūs vērtējat: The e Hardware Verification Language
Jūsu novērtējums:

Goodreads atsauksmes

221,75 € 369,58 €