Response Data Compression Techniques in Digital Circuit Testing: Study and Evaluation - Jaber Al-Balushi,Afaq Ahmad
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Today, digital logic circuits are essential embedded parts of devices that are critically important due to impact on public safety. Such devices include transportation, human implants and critical systems¿ management where Fault-Tolerant (FT) concept is the bottom line. To implement the concept of FT it is essential to test the system accurately to measure all the critical parameters of a dependable system. ... Pilns apraksts
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Aprašymas
Today, digital logic circuits are essential embedded parts of devices that are critically important due to impact on public safety. Such devices include transportation, human implants and critical systems¿ management where Fault-Tolerant (FT) concept is the bottom line. To implement the concept of FT it is essential to test the system accurately to measure all the critical parameters of a dependable system. Challenges of testing has become more difficult due to ubiquitous and complexity of digital systems. Exhaustive testing is impossible and ATEs are not commonly affordable that led to the design concepts of DFT and BIST techniques. Due to the problems of storing huge response data the data compression techniques (RDC) like One's Count, Transition Count, Syndrome Testing, Walsh Spectra Coefficients, Signature Analysis, etc. are used in practicing testing. However, the problems of Aliasing are inevitable in RDC techniques. Embodied in this book is the study and evaluations of the effectiveness of various RDC techniques while applied individually. The results of extended study and evaluations of combinations of different RDC techniques are also part of the contents of the book.
Vairāk informācijas
| Autors | Jaber Al-Balushi, Afaq Ahmad |
|---|---|
| Izdevējs | LAP LAMBERT Academic Publishing |
| Izlaides gads | 2014 |
| Vāka tips | Mīkstais vāks |
| EAN | 9783659239618 |