Implementation of Variable Latency Adders in Asynchronous Circuits: Using Speculative Completion Techniques - Ali Sayyed
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Asynchronous circuit design is enjoying resurgence in the digital world, with many recent technical and practical advancements and improvements. The advantages of asynchronous systems over synchronous systems are promising. The opportunity to implement high performance data-paths is very attractive by exploiting the fact that most data-path modules have data dependent delays. In other words they compute the ... Pilns apraksts
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Aprašymas
Asynchronous circuit design is enjoying resurgence in the digital world, with many recent technical and practical advancements and improvements. The advantages of asynchronous systems over synchronous systems are promising. The opportunity to implement high performance data-paths is very attractive by exploiting the fact that most data-path modules have data dependent delays. In other words they compute the result faster than worst case under many input combinations. Therefore making the common case fast, asynchronous data-paths have the potential to outperform synchronous designs on average inputs. This book explains the performance advantage that can be achieved by dynamically selecting the matched delay in a bundled-data setting. It presents the implementation and analysis of a method for the design of high performance asynchronous adders called ¿speculative completion¿ on six different 32 and 16 bit adders. The analysis on random data indicates that speculative completion yields signi¿cant performance improvements. The book describes the implementation details and the comparisons of results along with the final conclusions.
Vairāk informācijas
| Autors | Ali Sayyed |
|---|---|
| Izdevējs | LAP LAMBERT Academic Publishing |
| Izlaides gads | 2014 |
| Vāka tips | Mīkstais vāks |
| EAN | 9783659530265 |