Bezmaksas piegāde pasūtījumiem virs 29€

  • check 10+ miljoni grāmatu
  • check Jaunumi katru dienu
  • check Vairāk nekā 1 miljons klientu mums uzticas
  • check Labas cenas un atlaides
  • check Piegāde visā Eiropā

Formal Equivalence Checking and Design Debugging - Shi-Yu Huang,Kwang-Ting (Tim) Cheng

angļu valoda
1998-06-30
213,43 € 304,90 €

-30% ar kodu BOOKS

Piegādātāja noliktavā

Piegāde 17-23 darba dienu laikā

30 dienu atgriešanas politika

Formal Equivalence Checking and Design Debugging covers two major topics in design verification: logic equivalence checking and design debugging. The first part of the book reviews the design problems that require logic equivalence checking and describes the underlying technologies that are used to solve them. Some novel approaches to the problems of verifying design revisions after intensive sequential tra ... Pilns apraksts

Jums varētu patikt arī

Aprašymas

Formal Equivalence Checking and Design Debugging covers two major topics in design verification: logic equivalence checking and design debugging. The first part of the book reviews the design problems that require logic equivalence checking and describes the underlying technologies that are used to solve them. Some novel approaches to the problems of verifying design revisions after intensive sequential transformations such as retiming are described in detail. The second part of the book gives a thorough survey of previous and recent literature on design error diagnosis and design error correction. This part also provides an in-depth analysis of the algorithms used in two logic debugging software programs, ErrorTracer and AutoFix, developed by the authors. From the Foreword: `With the adoption of the static sign-off approach to verifying circuit implementations the application-specific integrated circuit (ASIC) industry will experience the first radical methodological revolution since the adoption of logic synthesis. Equivalence checking is one of the two critical elements of this methodological revolution. This book is timely for either the designer seeking to better understand the mechanics of equivalence checking or for the CAD researcher who wishes to investigate well-motivated research problems such as equivalence checking of retimed designs or error diagnosis in sequential circuits.' Kurt Keutzer, University of California, Berkeley

Vairāk informācijas

Autors Shi-Yu Huang, Kwang-Ting (Tim) Cheng
Izdevējs Springer US
Series Frontiers in Electronic Testing
Izlaides gads 1998
Vāka tips Cietais vāks
EAN 9780792381846
Rakstiet savu atsauksmi
Jūs vērtējat: Formal Equivalence Checking and Design Debugging
Jūsu novērtējums:

Goodreads atsauksmes

213,43 € 304,90 €